The present invention relates to a data transfer circuit, and more particularly, to a data transfer circuit with a simple configuration and a semiconductor memory device including the data transfer circuit.
When a read command is input from a data processor, such as a central processing unit (CPU) or a graphic processing unit (GPU), a semiconductor memory device outputs data stored in a cell corresponding to an address which is input from the data processor. In addition, when a write command is input from the data processor, the semiconductor memory device stores data in a cell corresponding to an address which is input from the data processor. Such read and write operations of the semiconductor memory device are performed at a high speed.
In general, as the speed of performing the read and write operations increases, the semiconductor memory device is considered to have better operating performance. Particularly, in a semiconductor memory device for processing a large quantity of data such as image data, the speed of outputting the data is an important indicator of performance. In addition, as the data output from the semiconductor memory device are transferred more accurately, the system can operate more reliably.
FIG. 1 is a timing diagram showing a read operation of the semiconductor memory device. FIG. 1 illustrates clocks and data of a high speed semiconductor memory device, which is embodied, for example, as a DRAM connected to a GPU in a system for processing graphic data.
Referring to FIG. 1, the semiconductor memory device outputs data (DRAM DATA) corresponding to a read command of the GPU in synchronization with a rising edge and a falling edge of a memory clock (DRAM CLOCK). In addition, the GPU reads the data in synchronization with a rising edge and a falling edge of a graphic clock (GPU CLOCK). For the GPU to receive the data accurately, the rising and falling edges of the GPU clock should be within an effective window of the data output from the semiconductor memory device. The effective window is represented by ‘UI’ in FIG. 1.
During the data transfer, data delay DELAY may occur due to physical factors between the semiconductor memory device and the GPU. Although the semiconductor memory device outputs data in synchronization with an edge of the memory clock (DRAM CLOCK), in order to allow the GPU to receive the data accurately, the edge of the graphic clock (GPU CLOCK) should be within the effective window of the transferred data, preferably at a center of the effective window of the transferred data. Therefore, it is preferable that a phase difference between the memory clock (DRAM CLOCK) and the graphic clock (GPU CLOCK) is 0.5×UI, and a data delay is DELAY+0.5×UI. Because of the different clock environments between the semiconductor memory device and the GPU, the data being transferred are mismatched with a clock for recognizing the data, that is, a data trigger signal.
In order to solve the mismatch and provide a stable operation, a system including the semiconductor memory device predefines a delay time between the semiconductor memory device and the GPU. For example, separate reference signals such as a read strobe signal (RDQS) and a write strobe signal (WDQS) are predefined.
However, because parameters according to the definition and related information are predefined, unexpected variations of operation environments may hinder the normal data transfer in actual operation. Particularly, in a high speed system, as the effective data window becomes smaller and more data are transferred between a semiconductor memory device and a GPU, the stability of the data transfer is decreased.
Recently, a semiconductor memory device and a GPU perform data training to solve such problems and perform high speed data transfer. The data training is a technology for controlling skew between data using a predetermined training pattern between a controller and a semiconductor memory device to stably transfer data for read and write operations.
Recently proposed graphic semiconductor memory devices transfer data at a high speed over 4 Gbps, with such graphic semiconductor memory devices performing a data training to improve reliability in high speed operation.